The present invention relates to methods for retiming VLSI systems and specifically VLSI systems which contain precharged circuit structures and/or gated clock signals.
Due to the tangible speed, power, and area benefits of circuit structures that utilize precharging techniques and/or gated clock signals, both are common in high-performance VLSI designs. Prior methods of achieving retiming (i.e. optimizing the placement of latches) have not addressed the peculiarities of precharged circuit structures and gated clock signals and therefore, have not been applicable to many non-ASIC VLSI systems.
The present invention concerns a method which is capable of use with precharged circuit structures and gated clock signals and is applicable to the retiming of "full custom" VLSI designs. While the invention is described in conjunction with retiming, the methods are also applicable to solving the problem of timing verification. That is, the results are based upon a general set of "timing" constraints which is directly applicable to circuits containing precharged circuit structures and gated clock signals.
The fabrication of digital MOS/VLSI designs whose area and power dissipation are as low as possible often results in the use of "precharged" circuit structures and "gated" clock signals. For example, savings in area and power dissipation can frequently be realized by replacing combinational logic blocks with precharged circuit structures, such as domino logic. Savings can also be realized by using combinational logic blocks to selectively prevent clock pulses from reaching particular clocked storage elements. Due to the importance of minimizing area and power dissipation, many full-custom VLSI systems, such as microprocessors, make extensive use of such precharged structures and gated clock signals.
Retiming is the process of optimizing the placement of latches with respect to some performance parameter, generally clock period. Previous retiming techniques are not directly applicable to circuits that utilize gated-clock signals and/or precharged circuit structures because these techniques do not consider the additional timing constraints that such structures impose. This inability to handle gated clocks and precharged circuit structures prevents previous methods for retiming circuits from being applied to a variety of high-performance designs.